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www.fairchildsemi.com rev. 1.2.2 12/7/01 features ? 3-channels ? 100/140/175 ms/s conversion rate ? programmable clamps ? adjustable gain and offset ? internal reference voltage ?i 2 c/smbus compatible serial port ? pin compatible with ad9884a applications ? flat panel displays and projectors ? rgb graphics processing description as a fully integrated analog interface, the fms9884a can digi- tize rgb graphics with resolutions up to 1600 x 1200/65hz refresh or 1600 x 1200/85hz using alternate pixel sampling. adc sampling clock can be derived from either an external source or incoming horizontal sync signal using the internal pll. output data is released through either one port at full rate or both ports, each running at half-rate. setup and control is via registers, accessible through an smbus/i 2 c compatible serial port. input amplitude range is 500C1000mv with either dc or ac coupling. lower reference of ac coupled inputs is estab- lished with input clamps that are either internally generated or externally provided. common to the three channels are clamp pulses, a bandgap reference voltage and clocks derived from a pll or an external source. digital data levels are 2.5C3.3 volt cmos compliant. power can be derived from a single +3.3 volt power supply. for 175 mhz applications see special v pll requirements. package is a 128-lead mqfp. performance speci?cations are guaran- teed over 0c to 70c range. product number speed fms9884akac100 108 ms/s fms9884akac140 140 ms/s FMS9884AKAC175 175 ms/s block diagram clamp a/d converter a/d converter a/d converter gain & offset switch clamp gain & offset switch clamp gain & offset switch dra 7-0 dga 7-0 dba 7-0 rpd 7-0 gpd 7-0 bpd 7-0 r in g in b in a 0 a 1 drb 7-0 dgb 7-0 dbb 7-0 control sda scl pwrdn pll sync stripper timing generator hsin acs in coast xck lpf pxck hs dcs out dck dck hsout invsck vrefin vrefout reference clamp iclamp sck fms9884a graphics digitizer 3x8-bit, 108/140/175 ms/s triple video a/d converter with clamps
product specification fms9884a 2 rev. 1.2.2 12/7/01 architectural overview three separate digitizer channels are controlled by common timing signals derived from the timing generator. a/d clock signals can be derived from either a pll or an external clock xck. with the pll selected, a/d clocks track the incoming horizontal sync signal connected to the hsin input. setup is controlled by registers that are accessible through the serial interface. conversion channels typical rgb graphics signals, r in , g in , b in are ground ref- erenced with 700mv amplitude. if a sync signal is embedded then the usual format is sync on green with the sync tip at ground, the black level elevated to 300mv and peak green at 1000mv. ac coupled video signals must be level shifted to establish the lower level of the conversion range by clamping to the black level of the back porch (see figure 1). clamp pulses are derived from internal timing and control logic or from the external clamp input. figure 1. clamping to the back-porch gain and offset gain and offset registers serve two functions: adjustment of contrast and brightness by setting rgb values in tandem; matching the gain and offsets between channels, by setting rgb values individually to obtain the same output levels. a/d conversion range can be matched to the amplitude of the incoming video signal by programming gain registers gr, gg and gb, which vary sensitivity (lsb/volt) over a 2:1 range. incoming video signal amplitudes varying from 0.5 to 1.0 volt can be accommodated. input offset voltage of each converter is programmable in 1 lsb steps through the 6-bit osr, osg and osb registers. range of adjustment is equivalent to C31 to +32 lsb. a/d converter each a/d converter digitizes the analog input into 8-bit data words. latency is 5C6 1 / 2 clock cycles, depending upon the data out format. v refin is the source of reference voltage for the three a/d converters. v refin can be connected to either the internal bandgap voltage, v refout or an external voltage. output data con?uration output data number format for each channel is binary: 00 cor- responds to the lowest input; ff corresponds to the highest input. data can be released in either of two timing formats: 1. single 8-bit port at pixel rates up to 175ms/s. 2. dual 8-bit ports, each running at half the conversion rate. maximum rate is 88ms/s per port. data streams may be parallel or interleaved. timing and control timing and control logic encompasses the timing generator, pll and serial interface. timing generator all internal clock and synchronization signals are generated by the timing generator. master clock source is either the pll or the external clock input, xck. bit xcksel selects the master clock source. two clocks are generated. sampling clock, sck is supplied to all three a/d converters. phase of sck can be adjusted in 32 11.25 degree phase increments using the 5-bit phase register. dck is the output data clock. dck and dck are supplied as outputs for synchronizing data transfer from the digitizer outputs. horizontal sync applied to the input, hs in is propagated by the timing and control to the hs out output with a delay that aligns leading and trailing edges with the output data. phase locked loop with a horizontal sync signal connected to the hsin input pin, the pll generates a high frequency internal clock signal, pxck that is fed to the timing and control logic. frequency of pxck is set by the register programmable pll divide ratio, plln. coast is an input that disables the pll lock to the horizontal sync input, hsin. if hsin is to be disregarded for a period such as the vertical sync interval, coast allows the vco frequency to be maintained. omission of horizontal sync pulses during the vertical interval can cause tearing at the top of a picture, if coast is not used. two pixels per clock mode is set by programming the pll to half the pixel rate. by toggling the invck pin between frames, even and odd pixels can be read on alternate frames. serial interface registers are accessed through an i 2 c/smbus compatible serial port. four serial addresses are pin selectable. r in , g in , b in iclamp
fms9884a product specification rev. 1.2.2 12/7/01 3 pin assignments (128-lead mqfp (ka) package) 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 gnd vddo dck dck hsout dcsout gnd vddo gnd gnd gnd vdda pwrdn vrefout vrefin vdda 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 vddo gnd gnd gnd vddp gnd vddp gnd nc lpf xck vddp gnd coast hsin gnd 95 94 93 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 drb0 drb1 drb2 drb3 drb4 drb5 drb6 drb7 vddo gnd dga0 dga1 dga2 dga3 dga4 dga5 dga6 dga7 vddo gnd dgb0 dgb1 dgb2 dgb3 dgb4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 nc nc nc vdda gnd gnd rin vdda gnd vdda vdda gnd gnd acsin gin vdda gnd vdda vdda gnd gnd bin vdda gnd vdda 74 73 72 71 70 69 68 67 66 65 102 101 100 dgb5 dgb6 dgb7 vddo gnd dba0 dba1 dba2 dba3 dba4 dba5 dba6 dba7 26 27 28 29 30 31 32 33 34 35 36 37 38 gnd invsck clamp sda scl a0 a1 vddp vddp gnd nc nc nc 103 104 105 106 107 108 109 110 111 112 gnd vddo dra7 dra6 dra5 dra4 dra3 dra2 dra1 dra0 64 63 62 61 60 59 58 57 56 55 vddo gnd dbb0 dbb1 dbb2 dbb3 dbb4 dbb5 dbb6 dbb7
product specification fms9884a 4 rev. 1.2.2 12/7/01 pin assignments no. name no. name no. name no. name 1nc33v ddp 65 dba 7 97 drb 5 2nc34v ddp 66 dba 6 98 drb 4 3 nc 35 gnd 67 dba 5 99 drb 3 4v dda 36 nc 68 dba 4 100 drb 2 5 gnd 37 nc 69 dba 3 101 drb 1 6 gnd 38 nc 70 dba 2 102 drb 0 7r in 39 gnd 71 dba 1 103 gnd 8v dda 40 hsin 72 dba 0 104 v ddo 9 gnd 41 coast 73 gnd 105 dra 7 10 v dda 42 gnd 74 v ddo 106 dra 6 11 v dda 43 v ddp 75 dgb 7 107 dra 5 12 gnd 44 xck 76 dgb 6 108 dra 4 13 gnd 45 lpf 77 dgb 5 109 dra 3 14 acs in 46 nc 78 dgb 4 110 dra 2 15 g in 47 gnd 79 dgb 3 111 dra 1 16 v dda 48 v ddp 80 dgb 2 112 dra 0 17 gnd 49 gnd 81 dgb 1 113 gnd 18 v dda 50 v ddp 82 dgb 0 114 v ddo 19 v dda 51 gnd 83 gnd 115 dck 20 gnd 52 gnd 84 v ddo 116 dck 21 gnd 53 gnd 85 dga 7 117 hs out 22 b in 54 v ddo 86 dga 6 118 dcs out 23 v dda 55 dbb 7 87 dga 5 119 gnd 24 gnd 56 dbb 6 88 dga 4 120 v ddo 25 v dda 57 dbb 5 89 dga 3 121 gnd 26 gnd 58 dbb 4 90 dga 2 122 gnd 27 invsck 59 dbb 3 91 dga 1 123 gnd 28 clamp 60 dbb 2 92 dga 0 124 v dda 29 sda 61 dbb 1 93 gnd 125 pwrdn 30 scl 62 dbb 0 94 v ddo 126 v refout 31 a 0 63 gnd 95 drb 7 127 v refin 32 a 1 64 v ddo 96 drb 6 128 v dda
fms9884a product specification rev. 1.2.2 12/7/01 5 pin descriptions pin name pin no. type/value pin function description converter channels r in , g in , b in 7, 15, 22 input analog inputs. dra 7-0 105?12 output red channel port a data output. full rate/half rate, interleaved/ parallel data depending upon selected mode. drb 7-0 95?02 output red channel port b data output. active for dual port mode only with interleaved/parallel outputs. high impedance when inactive. dga 7-0 85?2 output green channel port a data output. see red channel port a. dgb 7-0 75?2 output green channel port b data output. see red channel port b. dba 7-0 65?2 output blue channel port a data output. see red channel port a. dbb 7-0 55?2 output blue channel port b data output. see red channel port b. timing generator clamp 28 input external clamp input. invsck 27 input invert sampling clock. inverts sck, the internal clock sampling the analog inputs. supports alternate pixel sampling mode for capture pixel rates up to 350ms/s. xck 44 input external clock input. enabled if register bit, xcksel = h. replaces pxck clock generated by pll. if unused, connect to ground through a 10k ? resistor. dck 115 output output data clock. clock for strobing output data to external logic. dck 116 output output data clock inverted. inverted clock for strobing output data to external logic. hsout 117 output horizontal sync output. reconstructed hsync delayed by fms9884a latency and synchronized with dck. leading edge is synchronized to start of data output. polarity is always active high. phase locked loop hsin 40 schmitt horizontal sync input. schmitt trigger threshold is 1.5v. a 5v source should be clamped at 3.3v or current limited to prevent overdriving esd protection diodes. coast 41 input pll coast. maintain frequency of pll output clock pxck, disregarding hsin. if horizontal sync is missing during the vertical sync interval, pxck clock frequency can be maintained by asserting coast. lpf 45 passive pll low pass filter. connect recommended pll filter to lpf pin. (see figure 19.) sync stripper acs in 14 analog composite sync input. input to sync stripper with 150mv threshold. dcs out 118 digital composite sync output. output from sync stripper. control sda 29 bi-directional serial port data. bi-directional data. scl 30 input serial port clock. clock input. a 0 31 input address bit 0. lower bit of serial port address. a 1 32 input address bit 1. upper bit of serial port address. pwrdn 125 input power down/output control. powers down the fms9884a and tri-states the outputs.
product specification fms9884a 6 rev. 1.2.2 12/7/01 addressable memory register map pin descriptions (continued) pin name pin no. pin function description power and ground v dda 4, 8, 10, 11, 16, 18, 19, 23, 25, 124, 128 adc supply voltages. provide a quiet noise free voltage. v ddp 33,34,43,48,50 pll supply voltage. most sensitive supply voltage. provide a very quiet noise free voltage. v ddo 54, 64, 74, 84, 94, 104, 114, 120 digital output supply voltage. decouple judiciously to avoid propagation of switching noise. gnd 5, 6, 9,12, 13, 17, 20, 21, 24, 26, 35, 39, 42, 47, 49, 51, 52, 53, 63, 73, 83, 93, 103, 113, 119, 121, 122, 123 ground. returns for all power supplies. connect ground pins to a solid ground plane. v refin 127 voltage reference input. common reference input to rgb converters. connect to vrefout, if internal reference is used. v refout 126 voltage reference output. internal band-gap reference output. tie to ground through a 0.1? capacitor. name address function default (hex) plln 11-4 00 pll divide ratio, msbs. plln + 1 = total number of pixels per horixontal line. 69 (1693) plln 3-0 01 pll divide ratio, lsbs. plln + 1 = total number of pixels per horizontal line. plln 3-0 stored in the four upper register bits 7-4. d0 (1693) gr 7-0 02 gain, red channel. adjustable from 70 to 140%. 80 gg 7-0 03 gain, green channel. adjustable from 70 to 140%. 80 gb 7-0 04 gain, blue channel. adjustable from 70 to 140%. 80 osr 5-0 05 offset, red channel. osr 5-0 stored in the six upper register bits 7-2. default value is decimal 32. 80 osg 5-0 06 offset, green channel. osg 5-0 stored in the six upper register bits 7-2. default value is decimal 32. 80 osb 5-0 07 offset, blue channel. osb 5-0 stored in the six upper register bits 7-2. default value is decimal 32. 80 cd 7-0 08 clamp delay. delay in pixels from trailing edge of horizontal sync. 80 cw 7-0 09 clamp width. width of clamp pulse in pixels. 80 config1 0a configuration register no. 1 f4 plln 3? x x x x x osr 5? x x osg 5? x x osb 5? x x
fms9884a product specification rev. 1.2.2 12/7/01 7 register de?itions pll con?uration register (0c) phase 7-0 0b sampling clock phase. phase 4-0 stored in upper register bits 7-3. phase sets the sampling clock phase in 11.25?increments. default value is decimal 16. 80 pllctrl 0c pll control 24 config2 0d configuration 00 0e reserved 0x 0f reserved 00 con?uration register 1 (0a) bit no. name type description 0 1 xcksel r/w external clock select. select internal clock source. 0: internal pll 1: xck input. 2 xclampol r/w external clamp polarity. select clamp polarity. 0: active l. 1: active h. 3 xclamp r/w external clamp select. select clamp source. 0: internally generated by pll referenced to hsin. 1: external clamp input. 4 coastpol r/w coast polarity. select coast input polarity. 0: active l. 1: active h. 5 hspol r/w hsin polarity. select horizontal sync input polarity. pll is locked to selected edge: 0: falling edge. 1: rising edge. 6 parallel r/w output data format. select format of data outputs. 0: interleaved. dck rising edge strobes port a data. dck rising edge strobes port b data. 1: parallel. rising edge of dck strobes port a and port b data. 7 demux r/w output data porting. data released at full rate through one port or through two half-rate ports. 0: single 8-bit port. 1: dual 8-bit ports. bit no. name type description 1-0 4-2 ipump 2-0 r/w charge pump current. selects charge pump current (?). (see table 5. charge pump current codes) 000: 50 001: 100 010: 150 011: 250 100: 350 101: 500 110: 750 111: 1500 name address function default (hex) phase 4? x x x
product specification fms9884a 8 rev. 1.2.2 12/7/01 con?uration register 2 (0d) test register (0f) 6-5 fvco 1-0 r/w vco frequency range. selects vco frequency range (mhz). 00: 20?0 01: 20?0 10: 80?20 11: 110?75 7 r/w reserved. 0: run. 1: (reserved). bit no. name type description 0 reserved. set to 0. 3-1 rev r revision number. die revision number. 4 outphase r/w output data phase. in the dual port mode, selects either odd (1, 3, 5, ? or even (2, 4, 6 ?) samples following the hsync leading edge to be emitted from port 1. 0: even samples to port a, odd samples to port b. 1: odd samples to port a, even samples to port b. 7-5 r/w reserved. set to 00. bit no. name type description 7-0 r/w reserved. after power-up, initialize this register with the default value 0x00. register 0f does not respond with an acknowledge during serial bus access. consequently, ack remains h instead of being pulled h. bit no. name type description functional description there are two major sections within the fms9884a digitizer: 1. analog-to-digital converter channels, one for each channel, rgb and the voltage reference. 2. timing and control comprising the pll, timing generator, sync stripper and serial interface. a/d converter channels each of the three rgb channels consists of: 1. a clamp to set the lower reference level of an ac coupled input. 2. gain and offset stages to tune the converter to input signal levels. 3. an analog-to-digital converter to digitize the analog input. 4. a commutating switch for dual port operation. analog inputs input signal range is 500 to 1000mv to support conversion of single-ended signals with a typical amplitude of 700mv p-p. with the clamp active, each input accommodates a negative 300mv excursion. inputs are optimized for a source resistance of 37.5 to 75 ? . to reduce noise sensitivity, the ultra-wide 500mhz input bandwidth may be reduced by adding a small series inductor prior to the 75 ? terminating resistor. see applications section. clamps if the incoming signals are not ground referenced, a clamp must be used to set the incoming video range relative to ground. prior to each a/d converter, each channel includes a clamp that allows a capacitively coupled input to be referenced to the a/d converter bottom reference voltage when the clamp pulse is active. source of the clamp signal is deter- mined by the xclamp bit. internal clamp timing is generated by the timing and con- trol block. position and width of the internal clamp pulse, iclamp are programmable through registers cd and cw. external clamp input is selected by register bit xclamp and the external clamp polarity selected through register bit xclampol. to disable the clamp for dc coupled inputs, set xclamp = 1 with either of these conditions: 1. xclampol = 0 with input clamp = h. 2. xclampol = 1 with clamp = l. best performance will be achieved with the clamp set active for most of the black signal level interval between the trail- ing edge of horizontal sync and the start of active video.
fms9884a product specification rev. 1.2.2 12/7/01 9 insuf?cient clamping can cause brightness changes at the top of the image and slow recovery from large changes in aver- age picture level (apl). recommended value of cd is 0x10 to 0x20 for most standard video sources. analog-to-digital converter figure 2 is a block diagram of the adc core with gain and offset functions. g 7-0 , os 5-0 , rgb in and pd 7-0 generically refer to the gain and offset register values, analog input and parallel data output of any rgb channel. core of the adc block is a high speed a/d encoder with dif- ferential inputs. within the a/d converter core are the fol- lowing elements: 1. differential track and hold. 2. differential analog-to-digital converter. setting the gain register value g 7-0 (gr 7-0 , gg 7-0 , gb 7-0 ), establishes the gain d/a converter voltage which is the a/d reference voltage. increasing video gain reduces the contrast of the picture since the number of output codes is reduced. conversion range is de?ned by the gain setting according to table 1. table 1. gain calibration a/d converter sensitivity is: offset is set through the single-ended to differential ampli?er which translates the ground referenced input to a differential voltage centered around a/d common mode bias voltage. the 6-bit offset d/a converter injects a current into r level with two components: 1. i bias to establish the a/d common mode voltage. 2. i offset to set the offset from the common mode level. voltage offset from the common mode voltage at the invert- ing input of the track and hold is: d/a converter gain tracks a/d gain with 1 lsb of offset cor- responding to 1 lsb of gain. increasing osr 5-0 , osg 5-0 , or osb 5-0 reduces brightness in the selected channel. data out- put from the a/d converter is: impact of the offset values osr 5-0 , osg 5-0 , and osb 5-0 is shown in table 2. table 2. offset calibration sampling clock phase adjustment picture quality is strongly impacted by the phase 4-0 value. if phase is not set correctly, any section of an image con- sisting of vertical lines may exhibit tearing. g 7-0 conversion range (mv) 0 500 66 h 700 ff h 1000 s 255 500 -------- - = 255 255 g 70 C + ---------------------------- - lsb mv ? ? ? os 5-0 output offset (decimal) 0 +31 1f h 0 3f h -32 v os os 50 C 31 C () 255 g 70 C + 255 ---------------------------- - 500 255 -------- - ? ? = ? ? d 70 C sv in ? os 50 C 31 C () C = ? figure 2. a/d converter architecture a/d d 7-0 rgb in + - d/a current d/a gain register offset register r level v os sck i bias + i offset v ref g 7-0 os 5-0 track & hold a/d core
product specification fms9884a 10 rev. 1.2.2 12/7/01 figure 3. internal sampling clock, sck timing phase rgbn pxck/xck sck r in g in b in dck d 7-0 figure 3 shows how an analog input, r in g in b in is sampled by the rising edge of sck after a delay phase from the ris- ing edge of either pxck or xck. sck can be delayed up to 32 steps in 11.25 increments by adjusting the register value, phase 4-0 . output data, dck and dck are delayed in tandem with sck relative to pxck or xck. there is a 5-5 1 / 2 clock latency between the data sample rgb n and the correspond- ing data out d 7-0 . ideally, incoming pixels would be trapezoidal with fast rise- times and the sampling edge of the a/d clock, sck would be positioned along the level section of the incoming pixel waveform as shown in figure 4. there is a narrow zone of uncertainly where sampling during pixel rise time would cause an error in the value of the a/d data output, d 7- 0, which is shown as a value, 0-255. figure 4. ideal pixel sampling in practice, high-resolution pixels have long rise-times. as shown in figure 5, there are narrow zones of serendipity when the pixel amplitude is level. samples are valid in these zones. figure 5. acceptable pixel sampling referring to figure 6, when the sample clock, sck has some jitter, if the sampling edge occurs anywhere within the zone of uncertainty where the pixel rise time is steep, there will be amplitude modulation of the digitized data, d 7-0 , due to the sampling clock jitter. to avoid corruption of the image, set- ting the value phase 7-0 is critical. phase 4-0 should be trimmed to position the sampling edge of sck within the zone of serendipity. figure 6. improper pixel sampling voltage references an on-chip voltage reference is generated from a bandgap source. v refout is the buffered output of this source that can be connected to v refin to supply a voltage reference that is common to the three converter channels. d 7-0 r in , g in , b in sck zones of uncertainty d 7-0 r in , g in , b in sck zones of serendipity d 7-0 r in , g in , b in sck zones of uncertainty
fms9884a product specification rev. 1.2.2 12/7/01 11 figure 7. output timing phase n t dh t do s0 d0 pxck/xck sc hsin k rgbin dck hsout dck d[7..0] figures 13 through 21 depict data output timing relative to the sampling clock and inputs for all modes. timing is refer- enced to the leading edge of hsin when the ?rs t sample is taken at the rising edge of sck. status of register bit out- phase, determines if even samples are directed the a-port and odd samples are directed to the b-port; or vice versa. note the timing of the hsout waveform: 1. hsout is always active high. 2. only the leading edge of hsout is active or selected by the hspol register bit. 3. hsout is aligned with dck. 4. trailing edge is linked to hsin. 5. if hsin does not terminate before mid-line, hsout is forced low. a 50% duty cycle indicates that hspol is incorrectly set. hs is the internal sync pulse generated from hsync. sck is the internal a/d converter sampling clock. output data transitions are synchronized with the falling edge of dck. output data should be strobed on the rising edge of dck. a 5 to 6.5 clock cycle delay must be ?ushed before valid data is available. alternate pixel sampling mode a logic h on the ckinv pin inverts the sampling phase of sck. in the alternate pixel sampling mode: 1. pll is run at half rate. sck, dck and dck are half rate. 2. ckinv is toggled between frames. (see figure 18) v refin , with a nominal voltage of 1.25v, is the source of the differential reference voltages for each a/d converter. reference voltages supplied to the differential inputs of the comparators in the a/d converters are derived from v refin . digital data outputs input horizontal sync, hsin and outgoing data, d[7..0] are resynchronized to the delayed sample clock, sck. output timing characteristics are de?ned in figure 7. latency of the ?rst pixel, n varies according to the mode: 1. single or dual output port. 2. interleaved or parallel output data. 3. 1-pixel or 2-pixel. levels are 3.3 volt cmos with the output supply variable between 2.5 and 3.3 v. pwrdn = l sets the outputs high-impedance. pwrdn = h enables the outputs.
product specification fms9884a 12 rev. 1.2.2 12/7/01 figure 8. odd and even pixels in a frame on one frame, even pixels are sampled. on the other, odd pixels are sampled. alternate pixel sampling is similar to interlacing used in broadcast video, except that the columns of pixels are inter- laced instead of lines. figure 9. odd pixels from frame 1 figure 10. even pixels from frame 2 figure 11. combined frames 1 and 2 output. figure 12. subsequent output combining frames 2 and 3 o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 figure 13. single port mode rgbin hsin pxck hs sck datack da 7-0 hsout p6 p0 p1 p2 p3 p4 p5 d6 d0 d1 d2 d3 d4 d5 p7 d7 5 pipe delay
fms9884a product specification rev. 1.2.2 12/7/01 13 figure 14. single port mode, alternate pixel sampling, (even pixels) figure 15. single port mode, alternate pixel sampling, (odd pixels) figure 16. dual port mode, interleaved outputs rgbin hsin pxck hs sck datack da 7-0 hsout p6 p0 p1 p2 p3 p4 p5 d2 d4 d6 5 pipe delay d0 p7 p6 rgbin p0 p1 p2 p3 p4 p5 d7 d1 d3 d5 hsin pxck hs sck datack da 7-0 hsout 5.5 pipe delay p7 p6 rgbin p0 p1 p2 p3 p4 p5 d6 d0 d1 d2 d3 d4 d5 hsin pxck hs sck datack da 7-0 hsout p7 d7 db 7-0 5 pipe delay
product specification fms9884a 14 rev. 1.2.2 12/7/01 figure 17. dual port mode, parallel outputs figure 18. dual port mode, interleaved outputs, alternate pixel sampling, (even pixels) figure 19. dual port mode, interleaved outputs, alternate pixel sampling, (odd pixels) p6 rgbin p0 p1 p2 p3 p4 p5 d1 d3 d5 hsin pxck hs sck datack da 7-0 hsout p7 d7 d0 d2 d4 d6 6 pipe delay p6 rgbin p0 p1 p2 p3 p4 p5 d0 d2 d4 d6 hsin pxck hs sck datack da 7-0 hsout db 7-0 5 pipe delay p7 p6 rgbin p0 p1 p2 p3 p4 p5 hsin pxck hs sck datack da 7-0 hsout db 7-0 d3 d1 d7 d5 p7 5.5 pipe delay
fms9884a product specification rev. 1.2.2 12/7/01 15 figure 20. dual port mode, parallel outputs, alternate pixel sampling, (even pixels) figure 21. dual port mode, parallel outputs, alternate pixel sampling, (odd pixels) p6 rgbin p0 p1 p2 p3 p4 p5 hsin pxck hs sck datack da 7-0 hsout db 7-0 d0 d4 d2 d6 6 pipe delay p7 p6 rgbin p0 p1 p2 p3 p4 p5 hsin pxck hs sck datack da 7-0 hsout db 7-0 d3 d7 d1 d5 6.5 pipe delay p7 timing and control timing and control logic encompasses the pll, timing generator and sync stripper. phase locked loop two clock types originate in the pll: 1. data clocks dck and dck . 2. internal sampling clock sck. dck and dck are used to strobe data from the fms9884a to following digital circuits. sck is the adc sample clock which has adjustable phase controlled through the phase register. dck and dck are phase aligned with sck. reference for the pll is the horizontal sync input, hsin with polarity selected by the hspol bit. frequency of the hs in input is multiplied by the value plln + 1 derived from the plln 11-4 and plln 3-0 registers. plln + 1 should equal the number of pixels per horizontal line including active and blanked sections. typically blanking is 20C30% of active pixels. divide ratios from 2C4095 are supported. sck, dck and dck run at a rate plln + 1 times the hs in frequency. the pll consists of a phase comparator, charge pump vco and n counter, with the charge pump connected through the lpf pin to an external ?lter. these elements must be pro- grammed to match the incoming video source to be captured. values of ipump and fvco for standard vesa timing parameters are shown in table 3. timing of many computer video outputs does not comply with vesa recommendations. plln should be optimized to avoid vertical noise bars on the displayed image. modes marked 2x are 2x-oversampled modes where the number of samples per horizontal line is doubled. to select this mode, the phase-locked loop divide ratio value must changed from pll 1x to: values of ipump and fvco are set through the pll con?guration register (0x0c). recommended external ?lter components are shown in figure 22. rf quality 10% ceramic capacitors with x7r dielectrc are recommended. pll 2x 2pll 1x 1 + () ? 1 C =
product specification fms9884a 16 rev. 1.2.2 12/7/01 vesa monitor timing standards and guidelines, september 17, 1998 * graphics sampled at 1 / 2 incoming pixel rate using alternate pixel sampling mode. table 3. recommended ipump and fvco values for standard display formats standard resolution refresh rate horizontal frequency sample rate fvco 1-0 ipump 2-0 vga 640 x 480 60 hz 72 hz 75 hz 85 hz 31.5 khz 37.7 khz 37.5 khz 43.3 khz 25.175 mhz 31.500 mhz 31.500 mhz 36.000 mhz 01 01 01 01 100 100 100 100 2x 640 x 480 720 x 400 60 hz 67 hz 72 hz 75 hz 70 hz 31.5 khz 35 khz 37.7 khz 37.5 khz 31.5 khz 50 mhz 31 mhz 63 mhz 72 mhz 56.6 mhz 01 01 01 01 01 100 100 100 100 100 svga 800 x 600 56 hz 60 hz 72 hz 75 hz 85 hz 35.1 khz 37.9 khz 48.1 khz 46.9 khz 53.7 khz 36.000 mhz 40.000 mhz 50.000 mhz 49.500 mhz 56.250 mhz 01 01 01 01 100 100 110 110 xga 1024 x 768 60 hz 70 hz 75 hz 80 hz 85 hz 48.4 khz 56.5 khz 60.0 khz 64.0 khz 68.3 khz 65.000 mhz 75.000 mhz 78.750 mhz 85.500 mhz 94.500 mhz 01 01 10 111 111 111 mac 1024 x 768 1152 x 870 60 hz 75 hz 75 hz 48 khz 60 khz 69 khz 64 mhz 80 mhz 100 mhz 01 10 10 111 111 111 sun 1152 x 900 66 hz 62 khz 93 mhz 10 111 hp 1280 x 1024 60 hz 63 khz 108 mhz 10 111 sxga 1280 x 1024 60 hz 72 hz 75 hz 85 hz 64.0 khz 78.1 khz 80.0 khz 91.1 khz 108.000 mhz 135.000 mhz 135.000 mhz 157.500 mhz 10 11 11 11 111 111 111 111 uxga 1600 x 1200 60 hz 65 hz 70 hz 75 hz 85 hz 75.0 khz 81.3 khz 87.5 khz 93.8 khz 106.3 khz 162.000 mhz 175.500 mhz 189.000 mhz* 202.500 mhz* 229.500 mhz* 11 11 111 111 figure 22. schematic, pll filter. loop performance is established by setting: 1. vco frequency range through fvco 1-0 . (see table 4) 2. charge pump current through ipump 2-0 . (see table 5) 3. external loop ?lter component values. vddp lpf c2 0.018 f c1 0.18 f r1 1.5k
fms9884a product specification rev. 1.2.2 12/7/01 17 setting sphase 4-0 selects the sampling phase of sck rela- tive to pxck in 32 steps of 11.25. phase of the output data, dck and dck is slaved to the sck phase. clock jitter is less than 5% of pixel period in all operating modes. at lower frequencies below 40mhz, the jitter rises but can be reduced by over-sampling at a 2x clock rate. data should be read out of one port using the dual port mode. see performance section for jitter speci?cations and plots. coast coast = h disables pll lock to hsin, while the vco frequency is retained. vco frequency remains stable over several lines without updates from hsin. coast can be connected directly to the vertical sync signal or supplied by the graphics controller. operation of coast is depicted in figure 23. hsout polarity is always positive. when coast = l, hsout tracks hsin (shown with postive polarity in figure 23): 1. hsout rising edge tracks hsin delayed by a few pixels. 2. hsout falling edge tracks the trailing edge of hsin with no delay. when coast = h, the pll ?ywheels, disregarding the incoming hsin references, while the hsout waveform depends upon the state of hsin. 1. if hsin = h: a.) hsout rising edge remains locked to the pll. b.) hsout trailing edge falls after 50% of the hsout period has expired. 2. hsin transitions: a.) hsout rising edge remains locked to the pll. b.) hsout falling edge is terminated by the trailing edge of hsin. 3. if hsin = l, then hsout = l timing generator timing and control logic generates: 1. internal sampling clock, sck. 2. output data clocks, dck and dck . 3. output horizontal sync, hs out . 4. internal clamp pulse, iclamp. with hspol set correctly, iclamp delay follows the trail- ing edge of horizontal sync in (hsin). delay is set by the cd register. width of iclamp is set by the cw register. range of cd and cw values is 1C255 pixels. table 4. vco frequency bands fvco 2-0 frequency range (mhz) kvco (mhz/v) 00 20 90 60 01 10 80 120 90 11 110 175 100 table 5. charge pump current levels ipump 2-0 current (?) 000 50 001 100 010 150 011 250 100 350 101 500 110 750 111 1500 figure 23. 50% timeout hsin coast hsout trailing edge terminates hsout
product specification fms9884a 18 rev. 1.2.2 12/7/01 sync stripper some video signals include embedded composite sync rather than separate horizontal and vertical sync signals, typically sync on green. composite sync is extracted from composite video at the acs in pin. when the acs in signal falls below a 150mv ground refer- enced threshold, sync is detected. composite sync output, dcs out re?ects the acs in sync timing with non-inverted cmos digital levels. power down pwrdn = l minimizes fms9884a power consumption. data outputs become high impedance. clocks generation is stopped. register contents are maintained. sync stripping and the internal voltage reference function. serial interface register access is via a 2-wire i 2 c/smbus compatible inter- face. as a slave device, the 7-bit address is selected by the a 1-0 pins (see table 6). serial port pins sda and scl com- municate with the host smbus/i 2 c controller which act as a master. since the serial control port is design to interface with 3.3v logic, the pins must be protected by series connected 150 ? resistors if sda and scl signals originate from 5v logic. (see applications section) table 6. serial interface address codes two signals comprise the bus: clock (scl) and bi-directional data (sda). when receiving and transmitting data through the serial interface, the fms9884a acts as a slave, responding only to commands by the i 2 c/smbus master. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda may change only when scl = l. an sda transition while scl = h is interpreted as a start or stop signal. a 1-0 7-bit address 00 4c 01 4d 10 4e 11 4f figure 24. serial bus: read/write timing figure 25. serialbus: typical byte transfer t buff sda scl t stah t dho t dsu t dal t dah t stasu t stosu sda scl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ack figure 26. serial bus: slave address with read/write bit a6 a5 a4 a3 a2 a1 a0 r/w\ ack sda scl
fms9884a product specification rev. 1.2.2 12/7/01 19 there are ?ve steps within an i 2 c/smbus cycle: 1. start signal 2. slave address byte 3. pointer register address byte 4. data byte to read or write 5. stop signal when the serial bus interface is inactive, scl = h and sda = h. communications are initiated by sending a start signal (figure 24, left waveform) that is a high-to-low transition on sda while scl is high. a start signal alerts all slaved devices that a data transfer sequence is imminent. as shown in figure 26, after a start signal, the ?rst eight bits of data comprise a seven b it slave address followed a single r/w bit (read = h, write = l) to set the direction of data transfer: read from; or write to the slave device. if the trans- mitted slave address matches the address of the fms9884a which set by the state of the add pin, the fms9884a acknowledges by pulling sda low on the 9th scl pulse (see figure 26). if the addresses do not match or the register being accessed is 0x0f, the fms9884a does not acknowledge. for each byte of data read or written, the msb is the ?rst bit of the sequence. data transfer via serial interface if a slave device, such as the fms9884a does not acknowl- edge the master device during a write sequence, sda remains high so the master can generate a stop signal. dur- ing a read sequence, if the master device does not acknowl- edge by bringing sda = l, the fms9884a interprets sda = h as end of data. sda remains high so the master can generate a stop signal (figure 24, right waveform). to write data to a speci?c fms9884a control register, three bytes are sent: 1. write the slave address byte with bit r/w = l. 2. write the pointer byte. 3. write to the control register indexed by the pointer. after each byte is written, the pointer auto-increments to allow multiple data byte transfers within one write cycle. data is read from the control registers of the fms9884a in a similar manner, except that two data transfer operations are required: 1. write the slave address byte with bit r/w = l. 2. write the pointer byte. 3. write the slave address byte with bit r/w = h 4. read the control register indexed by the pointer. after each byte is read, the pointer auto-increments to allow multiple data byte transfers within one read cycle. preceding each slave write, there must be a start cycle. following the pointer byte there should be a stop cycle. after the last read, there must be a stop cycle comprising a low-to-high transition of sda while scl is high. (see figure 24, right waveform) a repeated start signal occurs when the master device driving the serial interface generates a start signal without ?rst gener- ating a stop signal to terminate the current communication. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. serial interface read/write examples examples below show how serial bus cycles can be linked together for multiple register read and write access cycles. for sequential register accesses, each ack handshake ini- tiates further scl clock cycles from the master to transfer the next data byte. write to one register 1. start signal 2. slave address byte (r/w bit = low) 3. pointer byte 4. data byte to base address 5. stop signal write to four consecutive registers 1. start signal 2. slave address byte (r/w bit = low) 3. pointer byte 4. data byte to base address 5. data byte to (base address + 1) 6. data byte to (base address + 2) 7. data byte to (base address + 3) 8. stop signal read from one register 1. start signal 2. slave address byte (r/w bit = low) 3. pointer byte (= base address) 4. stop signal (optional) 5. start signal 6. slave address byte (r/w bit = high) 7. data byte from base address 8. stop signal read from four registers 1. start signal 2. slave address byte (r/w bit = low) 3. pointer byte (= base address) 4. stop signal (optional) 5. start signal 6. slave address byte (r/w bit = high) 7. data byte from base address 8. data byte from (base address + 1) 9. data byte from (base address + 2) 10. data byte from (base address + 3) 11. stop signal
product specification fms9884a 20 rev. 1.2.2 12/7/01 absolute maximum ratings (beyond which the device may be damaged) 1 notes: 1. functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operating conditions are not exceeded. 2. applied voltage must be current limited to specified range. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. 5. eiaj test method. operating conditions parameter min. typ. max. unit power supply voltages v cc (measured to gnd) -0.5 4 v digital inputs applied voltage (measured to gnd) 2 -0.3 v dda v forced current 3, 4 -5.0 5.0 ma analog inputs applied voltage (measured to gnd) 2 -0.5 v dda v forced current 3, 4 -10.0 10.0 ma digital outputs applied voltage (measured to gnd) 2 -0.5 v forced current 3, 4 -6.0 6.0 ma forced current 3, 4 -8.0 8.0 ma short circuit duration (single output in high state to ground) 1 second temperature junction 150 c lead soldering (10 seconds) 300 c vapor phase soldering (1 minute) 220 c storage -65 150 c electrostatic discharge 5 150 v parameter min. nom. max. units v dda adc power supply voltage 3.0 3.3 3.6 v v ddp pll power supply voltage 140 ms/s 3.0 3.3 3.6 v > 140 ms/s 3.4 3.5 3.6 v v ddo output power supply voltage 2.2 2.5 3.3 3.6 v t a ambient temperature, still air 0 70 c a/d analog input range, min. 500 mv p-p a/d analog input range, max. 1000 mv p-p
fms9884a product specification rev. 1.2.2 12/7/01 21 electrical characteristics 1 notes: 1. unless otherwise stated, 0 to 70 c 2. demux = 1; dck, dck load = 15 pf; data load = 5 pf. 3. for optimum performance, null the input offset by calibrating gain and offset (see firmware section under applications information). parameter conditions min. typ. max. unit power supply currents i dda supply current, adc operating, 25 c 210 270 ma i ddd supply current 2 , digital output operating, 25 c3040ma i ddp supply current, pll operating, 25 c5065ma p d power dissipation 0 to 70 c 950 1300 mw i pd power-down current 0 to 70 c1520ma p dd powered-down disspation 0 to 70 c5070mw digital inputs/outputs c i input capacitance 25 c3pf c o output capacitance 25 c7pf i ih input current, high 0 to 70 c-1+1a i il input current, low 0 to 70 c-1+1a v ih input voltage, high 0 to 70 c 2.5 v v il input voltage, low 0 to 70 c 0.8 v i ohd output current, high, data 0 to 70 c4ma i ohc output current, high, clock 0 to 70 c8ma i old output current, low, data 0 to 70 c4ma i olc output current, low, clock 0 to 70 c8ma v oh output voltage, high i oh = max., 0 to 70 cv ddo 0.1 v v ol output voltage, low (v dd3 )i ol = max., 0 to 70 c 0.1 v serial bus i/o v smih input voltage, high 0 to 70 c 2.5 v v smil input voltage, low 0 to 70 c 0.8 v v smol output voltage, low i smol = max. 0.1 v i smoh output current, high (open drain) 0 to 70 c-1+1a i smol output current, low 0 to 70 c4ma analog inputs i b input bias current 0 to 70 c-11a e os input offset voltage 3 0 to 70 c11mv reference output output voltage 0 to 70 c 1.15 1.25 1.35 v temperature coefficient 0 to 70 c 50 ppm/ c
product specification fms9884a 22 rev. 1.2.2 12/7/01 switching characteristics parameter conditions min. typ. max. unit analog-to-digital converters conversion rate 0 to 70 c 10 175 ms/s t skew data to clock skew 0 to 70 c -0.5 2.0 ns timing generator hsin input frequency 0 to 70 c 15 110 khz maximum pll clock rate fms9884akac100 0 to 70 c 108 mhz fms9884akac140 140 FMS9884AKAC175 175 minimum pll clock rate 0 to 70 c 20 mhz serial bus interface t dal scl pulse width, low 0 to 70 c 4.7 s t dah scl pulse width, high 0 to 70 c 4.0 s t stah sda start hold time 0 to 70 c 4.0 s t stasu scl to sda setup time (start) 0 to 70 c 4.7 s t stosu scl to sda setup time (stop) 0 to 70 c 4.0 s t buff sda stop hold time setup 0 to 70 c 4.7 s t dsu sda to scl data setup time 0 to 70 c 250 ns t dho sda to scl data hold time 0 to 70 c0 ns system performance characteristics parameter conditions min. typ. max. unit analog to digital converter e li integral linearity error 1 0 to 70 c -2.5 2.5 lsb e ld differential linearity error 1 0 to 70 c -1.0 +1.0 lsb missing codes 0 to 70 c0 input full scale matching 0 to 70 c 2 6 %fs 2 offset adjustment range 0 to 70 c 22 23.5 25 %fs 2 gain tempco 25 c 280 ppm/ c b w analog bandwidth, full power 25 c 500 mhz transient response 25 c2ns t ov over-voltage recovery time 25 c 1.5 ns phase locked loop t pp peak-to-peak pll jitter @ mhz 25.175 25 c 6.5 ns 31.5 4.1 40 3.3 49.5 2.3 78.75 1.5 108 1.0 135 0.8 162 0.7 175 0.8
fms9884a product specification rev. 1.2.2 12/7/01 23 notes: 1. calibrated to 700 mv input. 2. percentage of full scale (uncalibrated). figure 27. pixel clock jitter vs. frequency thermal jc resistance, junction-to-case 8.4 c/w ja resistance, junction-to-ambient 35 c/w system performance characteristics (continued) parameter conditions min. typ. max. unit 0 20 0 1 2 3 4 5 6 7 40 60 80 pixel clock (mhz) jitter (ns p-p) 100 120 140 160 180 200 applications information two applications circuits are reviewed: 1. ac coupled digitizer with clamp. 2. ac coupled digitizer with dual ported outputs and sync stripping. to minimize component count, use of the following on-chip circuits is recommended: 1. adc sampling clock. 2. clamp. 3. voltage reference 4. dual ported data outputs optimum pll con?guration register (address 0x0c) set- tings for typical graphics modes are listed in table 3. unless otherwise indicated, all modes are compliant with vesa speci?cations. for unlisted modes, values should be adjusted to optimize performance. by adjusting the values in the gain (gr, gg, gb) and offset (osr, osg, osb) registers, the input conversion range can be matched to the incoming analog signals. to use the fms9884a in applications where the pll clock frequency will exceed 140 mhz, the pll power supply voltage must be 3.4 v min. for applications up to and including 140 mhz, the pll supply can be 3.0 v min. ac coupled digitizer shown in figure 28 is an implementation of a video digitizer with ac coupled rgb inputs. horizontal sync input, hs is passed through a voltage divider which attenuates the 5.0 v logic high excursion to the 3.3 v high input level of the fms9884a. vertical sync is also attenuated to make the vsout level compatible with 3.3 v pixel processing fol- lowing the fms9884a. output data is three channel port a data only with a maxi- mum rate of 175ms/s 24-bit pixels. data is clocked out on the negative edge of dck. hsout de?nes the active video along a line, while incoming vertical sync, vsin is propa- gated as vsout to the output data to synchronize handling of digitized frames of output data. control is through the serial port with 150 ? resistors inserted to allow interfacing with 5v logic. if the serial bus is operates with 3.3v levels, these resistors are unnecessary.
product specification fms9884a 24 rev. 1.2.2 12/7/01 figure 28. schematic, vga digitizer, single-port outputs vdd vdda vddo vddp green ba1 ba0 ra3 ra6 ra0 ga0 ga4 ra4 ba7 ga7 ga1 ba3 ga3 ga5 ra5 ba5 ga6 ga2 red hs vsin ba2 ra2 ra1 ba6 ba4 ra7 blue c19 0.1 f r5 1k 75 r4 r3 75 c4 .047 f r1 75 c6 0.018 f 0.18 f c7 .047 f c1 c2 .047 f r2 1.5k j1 svga 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 u1 ad9884 1 2 3 37 38 118 60 62 15 22 44 28 59 36 46 7 61 55 56 57 58 27 29 30 31 32 40 45 41 111 95 96 97 98 99 100 101 10 2 112 105 106 107 108 109 110 65 66 67 68 69 70 71 72 75 76 77 78 79 80 81 82 92 85 86 87 88 89 90 91 127 126 125 115 116 117 33 34 43 48 50 14 nc1 nc2 nc3 nc5 nc6 dcsout db _ b2 db _ b0 gin bin ckext clamp db _ b3 nc4 nc7 rin db_ b1 db _ b7 db _ b6 db _ b5 db _ b4 clkinv sda scl a0 a1 hsin filt coast dr_a1 dr_b7 dr_b6 dr_b5 dr_b4 dr_b3 dr_b2 dr_b1 dr_b0 dr_a0 dr_a7 dr_a6 dr_a5 dr_a4 dr_a3 dr_a2 db _ a7 db _ a6 db _ a5 db _ a4 db _ a3 db _ a2 db _ a1 db _ a0 dg_b7 dg_b6 dg_b5 dg_b4 dg_b3 dg_b2 dg_b1 dg_b0 dg_a0 dg_a7 dg_a6 dg_a5 dg_a4 dg_a3 dg_a2 dg_a1 refin refout pwrdn datack datack hsout pvd pvd pvd pvd pvd acsin hsout sda ga[7..0] scl ra[7..0] vsout dck ba [ 7..0] 4 8 10 11 16 18 19 23 25 124 128 54 64 74 84 94 104 114 120 vd vdd vd vdd vd vdd vd vdd vd vdd vd vdd vd vdd vd vd vd vd vdd 47 42 39 35 13 17 20 21 24 26 49 51 52 53 63 73 83 93 103 11 1 1 1 1 1 21 22 23 3 9 12 9 5 6 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd r10 150 r11 150 r6 1k r9 10k r7 1.8k r8 1.8k vga source with dual ported outputs shown in figure 29 is a more complex implementation of a video digitizer. incoming rgb video has sync-on-green. output data is dual ported. coast is shown to free wheel the pll when horizontal sync is inactive or 2h pulse are present. rgb inputs signals are ac coupled to the fms9884a rgb inputs with the green input connected to the sync separator input, cvin. output data is three channel dual port data with a maximum rate of 70ms/s per port. port a data is synchronzed to the negative edge of dck. port b data transitions on: 1. positive edge of dck in the parallel data out mode. 2. negative edge of dck in the interleaved data out mode. dck and dck clocks should be timed to strobe data that is valid between transitions. composite sync from the sync stripper output csout is supplied to the hsync input as a reference for the internal pll. cssout contains horizontal and vertical sync signals that can be extracted by subsequent sync processing logic. if the vertical sync pulse omits horizontal sync or if serrations or equalizing pulses are present, then the sync processing logic should emit a coast signal to disengage the pll from the hsync input during the vertical sync interval. vertical and horizontal sync waveforms within cssout signal frame the active video area.
fms9884a product specification rev. 1.2.2 12/7/01 25 figure 29. schematic, vga digitizer, dual port outputs vadc vdd vpll bb6 green bb4 ba1 ba0 ra3 bb1 rb7 gb6 ra6 gb4 ra0 rb2 ga0 ga4 ra4 rb0 bb0 ba7 gb1 ga7 ga1 ba3 bb3 rb1 bb5 ga3 ga5 gb5 ra5 gb2 gb0 rb3 rb6 ba5 ga6 gb3 rb5 bb7 ga2 red rb4 ba2 gb7 ra2 ra1 ba6 bb2 ba4 ra7 blue c17 0.1 f r4 75 r3 75 c3 .047 f r1 75 c4 0.018 f c2 0.18 f c5 .047 f c1 .047 f r2 1.5k j1 svga 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 u1 ad98 84 1 2 3 37 38 118 60 62 15 22 44 28 59 36 46 7 61 55 56 57 58 27 29 30 31 32 40 45 41 111 95 96 97 98 99 100 101 102 112 105 106 107 108 109 110 65 66 67 68 69 70 71 72 75 76 77 78 79 80 81 82 92 85 86 87 88 89 90 91 127 126 125 115 116 117 33 34 43 48 50 14 nc1 nc2 nc3 nc5 nc6 dcsout db _ b2 db _ b0 gin bin ckext clamp db _ b3 nc4 nc7 rin d b_ b1 db _ b7 db _ b6 db _ b5 db _ b4 clkinv sda scl a0 a1 hsin filt coast dr_a1 dr_b7 dr_b6 dr_b5 dr_b4 dr_b3 dr_b2 dr_b1 dr_b0 dr_a0 dr_a7 dr_a6 dr_a5 dr_a4 dr_a3 dr_a2 db _ a7 db _ a6 db _ a5 db _ a4 db _ a3 db _ a2 db _ a1 db _ a0 dg_b7 dg_b6 dg_b5 dg_b4 dg_b3 dg_b2 dg_b1 dg_b0 dg_a0 dg_a7 dg_a6 dg_a5 dg_a4 dg_a3 dg_a2 dg_a1 refin refout pwrdn datack datack hsout pvd pvd pvd pvd pvd acsin dck \ sda rb[7..0] bb [ 7..0] ga[7..0] scl ra[7..0] gb[7..0] hsout dck ba [7..0] pwrdn\ coast 4 8 10 11 16 18 19 23 25 124 128 54 64 74 84 9 1 1 1 4 04 14 20 dv dv dv dv dv dv ddv ddv ddv ddv ddv ddv ddv ddv dv dv dv dv dv 47 42 39 35 13 17 20 21 24 26 49 51 52 53 63 73 83 93 103 11 1 1 1 1 1 21 22 23 3 9 12 9 5 6 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd printed wiring board design guidelines recommended strategy is to mount the fms9884a over a ground plane with carefully routed analog inputs and digital outputs. all connections should be treated as transmission lines to ensure that re?ections due to mismatches are mini- mized and ground return currents do not interfere with critical signals. analog inputs recommendations: 1. keep analog trace lengths short to minimize crosstalk. 2. terminate analog inputs with 75 ? resistors, placed close to the fms9884a analog inputs, r in , g in and b in . by matching transmission line impedances, re?ections will be minimized. 3. layout traces as 75 ? transmission lines. 4. avoid running analog traces near digital traces. due to the wide input bandwidth (500mhz) digital noise can easily leak into analog inputs. 5. if necessary, limit bandwidth by adding a ferrite bead in series with each rgb input as shown in figure 30. a fair-rite #2508051217z0 is recommended. further bandwidth reduction using a shunt 10pf capacitor may reduce snow (intensity noise) caused by hf noise riding on the rgb input. mismatches, re?ections and noise may cause ringing or distortion of the incoming video signals. 6. locate the pll ?lter clear of other signals.
product specification fms9884a 26 rev. 1.2.2 12/7/01 7. bypass the reference with a 0.1f capacitor to ground. figure 30. rgb input filter options digital i/o recommendations: 1. route digital i/o signals clear of analog inputs. 2. terminate clock lines to reduce re?ections. treat clock lines as transmission lines. 3. scale the hsin input to 3.3v, using a resistor network or a series 1 k ? resistor. 4. limit serial port inputs sda and sdl with 150 ? resistors connected directly to the pins. 5. if necessary terminate the hsin input with 330/220 ? . 6. if necessary, to reduce re?ections, emi or spikes add a 50C200 ? resistor at each data output pin. 7. to minimize noise within the fms9884a, restrict the capacitive load at the digital outputs to < 10pf. power and ground a schematic of the recommended power distribution is shown in figure 31. note that: 1. analog and digital circuits are layed out over a common solid ground plane. 2. each fms9884a pin is decoupled with a 0.1f capacitor. 3. a group of pins may be de-coupled through a common capacitor if no pin is more than 5 mm from the capacitor. 4. a separate regulated supply is used for the phase-locked loop power supply, v ddp . 5. capacitors are attached to each pll pin or pin-pair. r in , g in , b in r, g, b input r1 75 l1 bead c1 47 nf c2 10pf figure 31. recommended power distribution power input pin 50 pin 48 pin 43 pins 33, 34 vadc pins vdd pins c5 +c6 bead bead l2 l3 u2 rc1117-3.3 3 1 1 2 4 out in adj/gnd out out in adj/gnd out u3 rc1117-3.3 3 2 4 c4 c3 c2 0.01 f 0.1 f 0.01 f 0.1 f 10 f + + c26 10 f c25 10 f + c8 10 f c9 c7 0.1 f c10 0.1 f c11 0.1 f c12 0.1 f c13 0.1 f c14 0.1 f c15 0.1 f c16 0.1 f c17 0.1 f c18 0.1 f c19 0.1 f c20 0.1 f c21 0.1 f c22 0.1 f c23 0.1 f c24 0.1 f 0.1 f bead l1 vpll 1 out in adj/gnd out u3 rc1117-3.3 3 2 4 c1 0.1 f
fms9884a product specification rev. 1.2.2 12/7/01 27 physical placement of pll power supply decoupling compo- nents is critical. bearing in mind the following suggestions: 1. all components should be placed in close proximity to the fms9884a pins. 2. routing through vias should be avoided, if possible. 3. each v ddp /gnd pin pair: 33&34/35, 43/42, 48/47, and 50/49 should be decoupled with a 100C1000p/10f pair of capacitors (see figure 31). if board space is limited, use as many capacitor pairs as possible. 4. use fair-rite 274 301 9447 bead. firmware best performance can be achieved by correctly setting the fms9884a registers. here are some recommendations: 1. set the value of plln equal to the number of pixels to be sampled minus one. with this setting, the number of samples per horizontal line equals the number of pixels. if plln + 1 does not equal the number of pixels, there will be irregular intensities on text and an interference pattern on a vertical grill pattern. 2. calibrate offset and gain by ?rst setting each input to 0mv. then adjust osr, osg, and osb to set each rgb data output d 7-0 = 0x00. next with 700mv input, adjust gr, gg and gb so that each rgb data output d 7-0 = (same value), typically 240 decimal. 3. clamp registers, cd and cw, should be programmed to maximize the period of the clamp during the backporch, while not encroaching into the sync or active video periods. 4. phase must be trimmed to minimize onscreen snow (intensity noise) when a vertical grill pattern is displayed. 5. fvco must be set to encompass the incoming frequency range. 6. ipump must be set to minimize intensity noise. 7. to ensure correct power-on defaults, program all regis- ters including test register 0x0f, which must be set to 0x00 for normal operation. note that unlike registers 0x00 through 0x0d, register 0x0f does not acknowledge. the ack bit remains h instead of being pulled l.
product specification fms9884a 28 rev. 1.2.2 12/7/01 mechanical dimensions 128-lead mqfp (ka) package e e1 2 e2 d d2 d1/2 e a a2 a1 b base plane seating plane see lead detail -c- ccc c lead coplanarity notes: 1. 2. 3. 4. all dimensions and tolerances conform to ansi y14.5m-1994. dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254mm per side. "n" is the number of terminals. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm in excess of the "b" dimension at the maximum material condition. a 3.04 3.40 symbol millimeters min. typ. max notes a1 0.25 0.33 2.71 a2 2.57 2.87 d2 18.00 bsc 17.20 bsc 14.00 bsc 12.00 bsc e e1 e2 l 0.65 0.70 0.95 128 0.50 bsc 4 3, 5 d n e d1 20.00 bsc 22.60 bsc b 0.13 ccc 0.12 0.28 0 7 0 min. 1.60 ref. datum plane lead detail l .40 min. 0.13 r min. .13/.30 r
product specification fms9884a life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12/7/01 0.0m 006 stock#ds30009884 ? 2001 fairchild semiconductor corporation ordering information product number temperature range screening package package marking fms9884akac100 0 c to 70 c commercial 128 lead mqfp 9884akac100 fms9884akac140 9884akac140 FMS9884AKAC175 9884akac175 disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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